Power quality management: Engineering boundaries for voltage sags, UPS, and critical process continuity ( part 3)

3. Close the loop of standards, calculations, and verification at the tool end.

1. Recommendations for Key Design Parameters

The table below shows commonly used engineering design windows for advanced fabs. Specific projects must be based on local power grid conditions, tool manufacturer hook-up specifications, insurance/fire protection requirements, current SEMI standards, and the fab’s internal risk level.

2. UPS energy saving cannot be achieved by simply switching to “Eco mode”.

The energy loss of a UPS can be estimated using the following formula:

If the efficiency of a 20 MW critical load is increased from 94% to 99%, the annual energy savings will be approximately:

There is significant potential for energy savings in this area, but efficiency cannot be sacrificed for immunity. TSMC’s publicly available case study shows that after analyzing voltage sag records in 2015-2016, it collaborated with UPS suppliers and UL to establish 116 validation projects according to SEMI F47, improving UPS efficiency from 94% to 99%; the publicly disclosed energy savings in 2016 were approximately 14.4 GWh. The key point of this case study is not “all fabs should operate in the same mode,” but rather to first demonstrate, using real-world grid disturbance records, F47 validation, and a tool risk checklist, that the efficient mode will not amplify process interruptions.

3. Acceptance should be done at the “tool end,” not just signed off in the electrical room.

Fab power quality verification should cover at least five levels: PCC, low-voltage side of main transformer, medium/low-voltage critical busbars, UPS/DVR output, and tool PDU or tool power box entry. Event replays should integrate power waveforms, FMCS trends, tool alarms, MES lot hold, and E10 downtime codes.

IV. FMEA should cover the chain failure of “Power – Utility – Tool – Product”.

Comparison of publicly disclosed practices by international peers

V. A set of implementable power quality management procedures

Establish a power disturbance database: covering at least PCC, main transformer, key medium and low voltage busbars, UPS/DVR outputs, and key tool PDUs. Sampling should be configured according to IEC 61000-4-30 Class A and synchronized with the same time.

Define the loss using the E10 language: Each trip should be encoded with downtime, engineering time, standby, non-scheduled, etc., instead of just writing “instantaneous stop”.

During the procurement phase, verification is included in F47 and tool-side validation: equipment suppliers provide test reports, the Fab retains the right to conduct on-site random testing, and key utility interfaces must also be included in the validation list.

Protection is tiered according to load consequences: L0 Safety, L1 Process Continuity, L2 Environmental Protection, L3 Controlled Shutdown, and L4 Non-critical, to avoid wasting UPS capacity on low-consequence loads.

Perform a recovery sequence drill: chiiller, PCW, vacuum, FFU, scrubber, CDA, N2 purge, AMHS, and critical tools must not simultaneously consume power.

Energy-saving optimization must be verified in a closed loop: UPS high-efficiency mode, DVR bypass, VFD sleep, and FFU speed reduction should all be evaluated based on their dynamic performance under disturbances, rather than just steady-state kWh.

Summarize

Power quality management in advanced fabs essentially involves transforming grid disturbances into calculable, verifiable, and reproducible process continuity issues. SEMI F47 provides a minimum immunity framework, but true fab-level design must cover tool-end waveforms, sub-fab utility, cleanroom differential pressure, safety interlocks, and recovery sequences. More UPS units are not necessarily better; the key is to allocate limited protection resources to L0/L1/L2 loads and validate them with real disturbance data. Energy-saving optimization is possible and has significant potential, but it must be preceded by completing F47 and field validation, as demonstrated in TSMC’s public case studies. The engineering implication for plant engineers is that every voltage sag should be treated as a system identification opportunity, ultimately leading to load grading, protection strategies, and FMEA updates.